Architecture of a programmable systolic array

Abstract

The architecture of a simple but programmable linear systolic array tuned to support a variety of symbolic computations is presented. The system, the Brown Systolic Array (B-SYS) is currently being implemented in CMOS. B-SYS demonstrates that programmable processor arrays may be made fully systolic with no need for local program memory or global instruction broadcasting. Any hazards introduced by the systolic instruction stream can be avoided using a processing phase concept. The application of these ideas results in a basic cell that is both simple and flexible, making it possible to build massively parallel, programmable systolic arrays.<>