A D-Band LNA Using a 22 nm FD-SOI CMOS Technology for Radar Applications

Abstract

A D-band low noise amplifier (LNA) has been fabricated in a 22 nm FD-SOI CMOS process for phased array radar applications. The LNA is composed of three identical stages of neutralized common source topology. A peak gain of 21 dB was measured with input and output matching (S11 and S22) better than −10 dB over the 131-162 GHz band. The power consumption of the LNA is 28 mW with expected noise figure (NF) of 6-6.5 dB and output P1dB of 3.8 dBm for a back-gate voltage of 0 V. Increasing the back-gate bias of the transistors to 1 V slightly increases gain and improves NF, but also allows optimizing power consumption vs. linearity tradeoff. Hence, improved NF of 5.5-6 dB and output P1dB of about 5 dBm at 140 GHz are expected, resulting also in an increased power consumption of 46 mW. The design consumes a core area of 200x100 µm2. While small signal S-parameters and power consumptions were validated in measurements, NF and linearity are yet to be measured.