A deep-submicron CMOS flow for general-purpose timing-detection insertion

Abstract

This paper introduces a design independent extension to RTL-to-GDS design-flows for seamless insertion of timing-detection flip-flops at critical paths of a digital CMOS standard-cell circuit. It is possible to detect timing-errors for general purposes at any critical path including enable-inputs of clock-gating cells with typically 15% area overhead for 20% endpoint coverage while maintaining DFT capability. To ensure matching of critical-path endpoints and detector cells 3 incremental place &route iterations are needed on average.