EKV Model for Bulk-Driven Circuit Design Using gmb/ID Method

Abstract

The paper addresses a development and application of EKV MOS transistor compact model with focus on the ultra low-voltage / ultra low-power analog integrated circuit (IC) design employing bulk-driven (BD) technique. The presented contribution can be viewed as an extension of standard EKV model application and as a contribution to ultra low-voltage IC design techniques. The paper compares the measured and extracted small-signal parameters of standalone transistor samples fabricated in 130 nm CMOS technology and the simulation results obtained using the proposed bulk-driven EKV v2.63 model and foundry-provided BSIM model v3.3. The transistor samples were analyzed with power supply of VDD = 0.4 V The paper also discusses the implementation of 3D graphs as a result of introducing another degree of freedom into the essential MOS transistor characteristics, while maintaining the ease of using the design hand-calculation with the original gm/ID approach.