Greedy Tuning Algorithm for Resource Scheduling of PISA Chips

Abstract

PISA (Protocol Independent Switch Architecture) is one of the mainstream programmable chip architectures, allowing users to define the functions and behaviors of the data plane with PISA language. The PISA chip optimizes robot design by providing flexible data processing capabilities, reducing the difficulty of robot maintenance, and enhancing the interoperability of the robot with other devices or systems. However, the application of the PISA chip faces two challenges. (1) Due to the complex dependencies and constraints in the chip, the current chip resource allocation algorithms waste a lot of pipeline stages when executing basic blocks of programs. (2) The time complexity of existing resource scheduling algorithms is high, which affects the efficiency of the chip. To tackle these challenges, we introduce a low-complexity greedy tuning algorithm to schedule the resource of the chip. Firstly, we unify the data dependencies and control dependencies as path constraints, which are derived from the program flowchart and variable read-write information. Then the initial feasible schedule scheme is constructed under the given constraints. Finally, we optimize the initial feasible solution by designing a new data structure, namely segment flowchart, which efficiently solves the resource-sharing problem among basic blocks within the same pipeline stage. In a practical example, basic blocks are successfully placed into the pipeline under given constraints, saving 14.9% of pipeline stages compared with the sequential approach. Our code and dataset are publicly available.