Effect of gate length on Negative Bias Temperature Instability of 32nm advanced technology HKMG PMOSFET

Abstract

Negative Bias Temperature Instability (NBTI) has become a key reliability concern in semiconductor industries as devices are scaled down. A simulation study had been done on 32 nm technology node PMOS using Synopsys TCAD Sentaurus simulator tool. This paper presents the effect of gate length on NBTI of 32 nm advanced technology high-k metal gate (HKMG) PMOSFET. The effect on the device parameters such as threshold voltage (Vth), drain current (Id) and the lifetime of the device had been studied and discussed in detail. It is found that NBTI is not highly dependent on gate length at low oxide field (Eox) while at higher Eox, longer gate length is shown to significantly affect the Vth degradation where Vth degradation in longer gate length is found to be lowered by 23.39% compared to the shorter.