Low Power Study on Trace Back and Reconstruction Modules for DNA Sequences Alignment Accelerator

Abstract

This paper presents the low power study on trace-back and reconstruction modules for DNA sequences alignment accelerator using ASIC design flow. The objectives of this paper are to construct trace-back and reconstruction modules, to perform low power analysis technique using frequency scaling and clock gating. Another objective is to implement the designs on ASIC. This paper focuses on the power consumption of the trace-back and reconstruction modules . As the number of DNA sequence database increases exponentially, it affects the performance of Smith-Waterman algorithm in computational complexity. Therefore, researchers have explored many methods to implement this algorithm by increasing the speed, reducing the power, minimizing the area and so on . The designs were written in Verilog language and verified on Xilinx FPGA design flow. Later, the designs were functionally verified in VCS, synthesized in DC and implemented on ICC. From the analysis, the designs' power consumptions remained constant at lower frequencies and started to increase exponentially when the clock period cross 20ns and lower. A clock gating technique was implemented on at clock period of 10ns for comparison. The results showed that the power consumption reduced up to 50 percent. The design was successfully implemented on ASIC design flow.