An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis

Abstract

Static timing analysis (STA), which is a part of design automation requires the generation and storage of delay values for combinational standard cells and the setup and hold time values for sequential cells at numerous corners in the form of a Look Up Table (LUT). This paper proposes a novel approach for LUT generation of sequential standard cells by developing a model for the setup time. The model uses the input data transition time (TR) and the output capacitance (CL) as its variables with two fitting parameters. The model's validity is verified through simulations in Cadence Virtuoso and using this model, it is shown that it reduces the number of simulations needed for the generation of a 6 × 6 LUT by 91.67%, while having an average percentage error of 2.28%. Also, the dependence of the fitting parameters on the sizing of the devices and their relation with process, voltage and temperature variations is shown and verified.