Accelerating Embedded Multimedia Applications with Versatile and Reconfigurable Instruction Fusion

Abstract

Continuously increasing demand for richer functionality, faster real-time communication, smaller feature size, longer battery life, more elevated security, and higher reliability is pushing the design for portable multimedia applications into the era where a single system is consisted of a general-purpose CPU interacting with several application-specific accelerating components and coprocessors to fulfill the ever diverse constraints imposed multi- directionally. The inter-component communication overhead, along with the engineering efforts required to integrate, verify, and validate such heterogeneous systems are scaled disproportionally as the complexity of such systems continue rising skyrocketedly. Moreover, due to limited instruction encoding space and the need to maintain backward compatibly in the future designs, designers are often forced to include only a very small subset of the total desired functionalities on chip, despite there can be more than sufficient silicon real estate to incorporate these specialized function units. This paper proposes a cost-effective technique of incorporating diverse functionalities into a single multi-purpose, streamlining acceleration unit, named Versatile Processing Unit (VPU), to replace the conventional ALU on a CPU. The proposed VPU can supply the general-purpose CPU with a rich set of streamlined operations, which may supersede some or even all of the heterogeneous cores. The superseded hardware components are removed to reduce the integration and communication overhead. The issues of limited instruction encoding space and future backward compatibility are resolved by our proposed dynamic instruction re-mapping technique, in which the instruction bit fields can be redefined on the fly to allow instruction space reuse at run time.