Impact of varying processor number for H264 in FPGA platform

Abstract

Multiprocessor architecture can be a solution to meet the increasing computational requirements for multimedia treatment algorithms such as video encoding. In this paper we study the effect of varying the processors number on resource utilization and system performance. We used Altera's NIOS II processors interconnected through Avalon bus. We vary the processors number from one to four and note its effect on the use of logic elements, DSP blocks and memory bits. We also note the change of the time execution of the Intra 16×16 chain of the H264/AVC encoder.