A Proficient Test Data Compression and Decompression System for Enhanced Test Competence in SOC Testing

Abstract

BIST is a systematic methodology capable of addressing many of the issues encountered when testing systems-on-chip. However, larger registers are required to handle the large amount of test information produced in each clock cycle, which has a significant impact on overall circuit performance. Huge data volume generally requires not only more memory but also a longer testing time. The proposed design develops a test compression method that employs both an efficient dictionary and creating and capturing value collection to dramatically reduce testing high memory requirements. Data compression reduces test data quantity without affecting overall system performance. This data compression method is applied to the test patterns generated by the BIST technique, and the compressed data is then applied to the module being tested Following that, a simple processor is designed. The concept of Null Conventional Logic is commonly used in the testing of the basic processing units in the processor designed.