A New Circuit Placement Program for FET Chips

Abstract

A new solution to the problem of automated placement of FET circuits has been implemented. This new approach automatically realizes a global solution to the problem yielding circuit location, circuit orientation, all cross column wires and blanks between circuits, thus eliminating many of the most tedious and error prone steps in physical design. The technique is based upon "natural selection" and obtains a solution using a series of sweeps through the columns evolving circuit position and cross column wiring assignments together. Scoring is done to minimize column peaks. This paper describes the novel aspects of the program including the control techniques, models and approach used. The program was developed for IBM's internal use in design.