A novel algorithm and architecture for a high-throughput VLSI implementation of DST using short pseudo-cycle convolutions

Abstract

Using a new input restructuring sequence and an appropriate reordering of the elements involved, a new VLSI algorithm that uses short length pseudo-cycle convolution structures for the VLSI implementation of discrete sine transform is presented. It uses a new parallel decomposition of discrete sine transform (DST) that leads to a high throughput VLSI implementation with a low hardware cost. The proposed algorithm is efficiently mapped onto two linear systolic arrays that have a modular and regular structure with a a low I/O cost and local and regular interconnections. Thus, an efficient VLSI implementation with high performances can be obtained.