Multi-core/tile Polymorphous Computing systems

Abstract

Polymorphous computing systems have been introduced in multi-core/tile architectures as a result of the DARPA Polymorphous Computing Architectures (PCA) program. We will review the state-of-the-art in multi-core systems, first by reviewing the PCA developed systems, and secondly by reviewing recently announced multi-core chips. The PCA-developed USC-ISI/Raytheon/Mercury MONARCH chip in addition to the general-purpose (post)-processing cores contains reprogrammable hardware for high-performance sensor-based (pre)-processing. This paper describes the application of polymorphous computing in embedded processing application domains. We will be particularly interested in the performance benefits gained from additional reconfigurable hardware in multi-core chips.