A Design Approach for Mac Unit Using Vedic Multiplier

Abstract

Machine learning problems have been efficiently solved by using Artificial Neural Networks (ANNs). The realization of neural networks on hardware have been shown to provide more significant advantages. In digital neural networks, the weight-input multiplication is an important step. In this paper, a comparative study between different configurations of Vedic multipliers and traditional array multipliers has been performed and further, the hardware implementation of the MAC unit has been performed using VHDL. MAC unit of ANN requires repetitive use of adders and multipliers. The aim behind the comparison is to obtain an alternative approach for the realization of the MAC unit of the neural network. This paper further proposes a network using the alternative multiplier in place of the normal array multiplier. The circuit implemented in this paper has been dedicated to a given data set. The testing accuracy by the network is achieved keeping in mind the precision of the multiplier.