Fault tolerant multiprocessor for digital switching systems

Abstract

A description is given of the fault-tolerant multiprocessor used in the D70 digital switching system (the main model in Japan). The multiprocessor architecture adopts function sharing as well as load sharing to achieve expansion of processing power efficiently using small but reliable VLSI processors. The fault-tolerance objectives of this multiprocessor are based on the failure magnitude dependence concept, which specifies that the requirement for reliability increases with system size. The multiprocessor combines a redundant configuration and the fail-soft principle to achieve the objectives. The fault recovery procedure comprises four stages of the hierarchical structure. Fault influence propagation is limited using the rationality test for interprocessor communication on the call processing level. Field experience shows that the objectives are satisfied.<>