Failure Analysis on Open Defect with Logic Time Sequence Analysis and Simulation Experiment Method

Abstract

FA (Failure Analysis) plays an important role in VLSI designing and manufacturing. In FA we usually handle the cases with open failure which we can't use FA tools (OBIRCH, EMMI and so on) to capture its location effectively. Therefore, it is an obstacle to improve success ratio of FA and reduce micro probing workload. In this paper, we proposed one FA idea to analyze gate floating when there were abnormal output, normal input and normal IV curves. And one LTS (logic time sequence) analysis and simulation experiment methods for open failure were introduced. Then, three real cases were shared with open contact, open via and open metal line defects respectively. The idea and method could not only provide novel and simple FA method for open failure, but also reduce micro probing workload and improve success ratio for FA case.