A Parallel-friendly Majority Gate to Accelerate In-memory Computation

J. Reuben, Stefan Pechmann
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引用次数: 8

Abstract

Efforts to combat the ‘von Neumann bottleneck’ have been strengthened by Resistive RAMs (RRAMs), which enable computation in the memory array. Majority logic can accelerate computation when compared to NAND/NOR/IMPLY logic due to it’s expressive power. In this work, we propose a method to compute majority while reading from a transistor-accessed RRAM array. The proposed gate was verified by simulations using a physics-based model (for RRAM) and industry standard model (for CMOS sense amplifier) and, found to tolerate reasonable variations in the RRAMs’ resistive states. Together with NOT gate, which is also implemented in-memory, the proposed gate forms a functionally complete Boolean logic, capable of implementing any digital logic. Computing is simplified to a sequence of READ and WRITE operations and does not require any major modifications to the peripheral circuitry of the array. The parallel-friendly nature of the proposed gate is exploited to implement an eight-bit parallel-prefix adder in memory array. The proposed in-memory adder could achieve a latency reduction of 70% and 50% when compared to IMPLY and NAND/NOR logic-based adders, respectively.
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一个并行友好的多数门加速内存计算
抵抗“冯·诺依曼瓶颈”的努力已经被阻性ram (rram)所加强,它可以在存储器阵列中进行计算。多数逻辑与NAND/NOR/IMPLY逻辑相比,由于其表达能力,可以加速计算。在这项工作中,我们提出了一种在从晶体管访问的RRAM阵列读取时计算多数数的方法。通过使用基于物理的模型(用于RRAM)和工业标准模型(用于CMOS感测放大器)的仿真验证了所提出的门,并且发现可以容忍RRAM电阻状态的合理变化。与同样在内存中实现的非门一起,所提出的门构成了一个功能完整的布尔逻辑,能够实现任何数字逻辑。计算被简化为一系列READ和WRITE操作,并且不需要对阵列的外围电路进行任何重大修改。利用所提出的门的并行友好特性,在存储器阵列中实现了一个8位并行前缀加法器。与基于暗示和基于NAND/NOR逻辑的加法器相比,所提出的内存加法器可以分别减少70%和50%的延迟。
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