Practical Approximations of Steiner Trees in Uniform Orientation Metrics

Abstract

The Steiner minimum tree problem, which asks for a minimum-length interconnection of a given set of terminals in the plane, is one of the fundamental problems in Very Large Scale Integration (VLSI) physical design. Although advances in VLSI manufacturing technologies have introduced additional routing objectives, minimum length continues to be the primary objective when routing non-critical nets, since the minimum-length interconnection has minimum total capacitance and occupies minimum amount of area. To simplify design and manufacturing, VLSI interconnect is restricted to a small number of orientations defining the so called interconnect architecture. Until recently, designers have relied almost exclusively on the Manhattan interconnect architecture, which allows interconnect routing along two orthogonal directions. However, non-Manhattan interconnect architectures – such as the Y-architecture, which allows 0, 120, and 240 oriented wires, and the X-architecture, which allows 45 diagonal wires in addition to the traditional horizontal and vertical orientations – are becoming increasingly attractive due to the significant potential for reducing interconnect length (see, e.g., [4, 5, 16, 22, 24, 25, 27]). A common generalization of interconnect architectures of interest in VLSI design is that of uniform orientation metric, or λ-geometry, in which routing is allowed only along λ ≥ 2 orientations forming consecutive angles of π/λ. The Manhattan, Y-, and X-architectures correspond to λ = 2, 3, and 4, respectively.