{"title":"A new FFT architecture for 4 × 4 MIMO-OFDMA systems with variable symbol lengths","authors":"A. Karachalios, K. Nakos, D. Reisis, H. Alnuweiri","doi":"10.1109/IIT.2009.5413367","DOIUrl":null,"url":null,"abstract":"We present a new FFT architecture for multi-input multi-output (MIMO) OFDMA wireless systems that require processing variable symbol lengths, ranging from 128 to 2048 complex points. The organization is based on 16 concurrent butterfly processing elements with each element computing a 128-point FFT by implementing an in-place technique. A novel processor-memory interconnection scheme allows the processing elements to operate in sets of k, 1 ≤ k ≤ 16, for completing FFT computations of size 128 × k, up to 2048 points. The architecture scales to support 4 × 4 MIMO-OFDMA operation. An FPGA implementation shows that the proposed organization requires 9995 slices on Xilinx Virtex-4 compared to 21624 slices of four parallel FFT architectures accomplishing the same task.","PeriodicalId":239829,"journal":{"name":"2009 International Conference on Innovations in Information Technology (IIT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Conference on Innovations in Information Technology (IIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIT.2009.5413367","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
We present a new FFT architecture for multi-input multi-output (MIMO) OFDMA wireless systems that require processing variable symbol lengths, ranging from 128 to 2048 complex points. The organization is based on 16 concurrent butterfly processing elements with each element computing a 128-point FFT by implementing an in-place technique. A novel processor-memory interconnection scheme allows the processing elements to operate in sets of k, 1 ≤ k ≤ 16, for completing FFT computations of size 128 × k, up to 2048 points. The architecture scales to support 4 × 4 MIMO-OFDMA operation. An FPGA implementation shows that the proposed organization requires 9995 slices on Xilinx Virtex-4 compared to 21624 slices of four parallel FFT architectures accomplishing the same task.