{"title":"Radiation hardening of commercial CMOS processes through minimally invasive techniques","authors":"J. Benedetto, D. Kerwin, J. Chaffee","doi":"10.1109/REDW.1997.629807","DOIUrl":null,"url":null,"abstract":"UTMC Microelectronic Systems has developed two minimally invasive radiation tolerant modules (RTMs) to harden a commercial CMOS process. The RTMs were successfully inserted into three commercial foundries. The results of UTMC's hardening effort clearly demonstrate that a total dose hardness of between 100 to 500 krad (SiO/sub 2/) can be achieved on a commercial CMOS process without significantly altering the commercial flow. This hardness level is from an initial set of experiments. Response factors from this first set of experiments have been identified which, when fully optimized, may increase the final total dose hardness level significantly.","PeriodicalId":328522,"journal":{"name":"1997 IEEE Radiation Effects Data Workshop NSREC Snowmass 1997. Workshop Record Held in conjunction with IEEE Nuclear and Space Radiation Effects Conference","volume":"90 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 IEEE Radiation Effects Data Workshop NSREC Snowmass 1997. Workshop Record Held in conjunction with IEEE Nuclear and Space Radiation Effects Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/REDW.1997.629807","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 17
Abstract
UTMC Microelectronic Systems has developed two minimally invasive radiation tolerant modules (RTMs) to harden a commercial CMOS process. The RTMs were successfully inserted into three commercial foundries. The results of UTMC's hardening effort clearly demonstrate that a total dose hardness of between 100 to 500 krad (SiO/sub 2/) can be achieved on a commercial CMOS process without significantly altering the commercial flow. This hardness level is from an initial set of experiments. Response factors from this first set of experiments have been identified which, when fully optimized, may increase the final total dose hardness level significantly.
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