A 66.1 Gbps single-pipeline AES on FPGA

Abstract

Targeting real-time encryption/decryption of high speed data communication, this paper proposes an FPGA-based high throughput AES design. The critical functions involved in AES are broken into elementary logic operations to gain the deep insight into the performance bottleneck. With respect to FPGA structures, a datapath with two balanced pipeline stages is determined for each of the encryption/decryption rounds. Meanwhile, a new key expansion scheme with additional nonlinear operations is proposed to increase the security of the AES implementation and is well matched to the two-stage pipelining datapath. The design is evaluated on various FPGA devices and is compared with several existing AES implementations. Results show that in terms of both throughput and throughput per slice the proposed AES design with single pipeline can overcome most existing designs and achieves a throughput of 66.1 Gbps on a latest FPGA device.