Dual-V/sub T/ SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 /spl mu/m technology generation

Abstract

Comparisons among different dual-V/sub T/ design choices for a large on-chip cache with single-ended sensing show that the design using a dual-V/sub T/ cell and low-V/sub T/ peripheral circuits is the best, and provides 10% performance gain with 1.2x larger active leakage power, and 1.6% larger cell area compared to the best design using high-V/sub T/ cells.