A New Design of HDB3 Encoder and Decoder Based on FPGA

Abstract

A new design of HDB3 encoder / decoder based on FPGA is proposed to deal with the high complexity and long output delay of the encoder and no error correction function of the decoder which have been implemented so far. The encoder has the function of converting a NRZ code sequence to a HDB3 sequence and the decoder, vice versa. Meanwhile the decoder can correct the errors in the received HDB3 sequence according to a certain rule. Synthesis reports show that the encoder and decoder are both simple–structured; Simulation results show that the encoder has a shorter output delay and the decoder has a better function of error detecting and correcting which greatly improves the reliability of the system.