Quang-Manh Duong, Quang-Kien Trinh, Hai D. Nguyen, Van‐Phuc Hoang, H. Vu, Dinh‐Ha Dao, D. Luong, Van-Toan Tran
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引用次数: 0
Abstract
This paper presents an effective approach forimplementing content address memory (CAM) based on Nonvolatile random-access memory (NV-RAM) technologies. Weused the 2T-2R bitcell structure implemented on a 65nmCMOS process with a special in-memory matching circuitfor realizing low-delay and energy-efficient lookup operations.The simulation results on Synopsys HSPICE indicate that theproposed CAM design can achieve a search error rate of0.03-4.61%, search energy per bit of 4.36-6.47 fJ, and anextremely small search latency varying from 0.11-0.12 nsdepending on the specific design configurations.
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