Functional test pattern generation for maximizing temperature in 3D IC chip stack

Abstract

In a stacked 3D Integrated Circuit (IC), the total power dissipated per unit surface area typically exceeds that of 2D ICs. This results in creation of a greater number of localized thermal hotspots in individual dies of the 3D IC. The location and temperature of these hotspots depend on the actual workload executing on a 3D IC. Since the power dissipation pattern from the applied workload may vary over time, the location and intensity of thermal hotspots may vary with it. The applied workload may be construed as consisting of phases, where the spatial power dissipation pattern remains constant over a phase and changes only from one phase to another. In this paper (i) we develop a thermal modeling scheme that predicts temperature profile at the end of a program phase, and use (ii) a novel Integer Linear Programming (ILP) formulation to arrange program phases to create worst case temperature at a target location. Experimental results show that, by taking the spatio-temporal effect into account, we can raise temperature of a hotspot much higher than what is possible from purely functional trace. Hotspot temperature maximization is important in design verification and testing.