A. Strey, N. Avellana, R. Holgado, R. Capillas, J. A. Fernández, E. Valderrama
{"title":"A configurable parallel neurocomputer","authors":"A. Strey, N. Avellana, R. Holgado, R. Capillas, J. A. Fernández, E. Valderrama","doi":"10.1109/ANNES.1995.499438","DOIUrl":null,"url":null,"abstract":"The paper presents the architecture of a new configurable parallel neurocomputer optimized for the high-speed simulation of neural networks. Its main system feature is the reconfigurability of a new arithmetical unit chip which supports several accuracies in all typical neural network operations. If the required accuracy is decreased the degree of parallelism inside the chip can be increased by a dynamical reconfiguration of the hardware resources. The system also offers a good scalability: for the simulation of large neural networks the system performance can easily be increased by using several arithmetical unit chips operating in parallel.","PeriodicalId":123427,"journal":{"name":"Proceedings 1995 Second New Zealand International Two-Stream Conference on Artificial Neural Networks and Expert Systems","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1995 Second New Zealand International Two-Stream Conference on Artificial Neural Networks and Expert Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ANNES.1995.499438","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The paper presents the architecture of a new configurable parallel neurocomputer optimized for the high-speed simulation of neural networks. Its main system feature is the reconfigurability of a new arithmetical unit chip which supports several accuracies in all typical neural network operations. If the required accuracy is decreased the degree of parallelism inside the chip can be increased by a dynamical reconfiguration of the hardware resources. The system also offers a good scalability: for the simulation of large neural networks the system performance can easily be increased by using several arithmetical unit chips operating in parallel.
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