Multiprocessor system architectures [Book Reviews]

Abstract

reviewed by Junusz Zuleu:skz, Em b7y-Riddle Aeronautical [Jniversity This book, part of the SunSoft Press series, is subtitled " A Technical Survey of Multi-processor/Multithreaded Systems Using Sparc, Multilevel Bus Architectures and Solaris (SunOS). " So, it covers only computer systems from Sun Microsystem:s Computer Corporation. Its purpose is " to bring together in one volume a coherent description of the elements that provide for the design and development of multiprocessor systems archi-tectures from Sun Microsystems. " It assumes that the reader understands computer architecture. As the subtitle suggests, the book progresses smoothly from processor hardware and its implementations to bus architectures, to low-level programming that includes threads and lightweight processes, and to complete systems. The book starts with general material on multiprocessing and on using Sun implementations. Ben Catanzaro correctly observes that because of physical limitations in malung chips faster, system performance will depend more and more on advances in computer architecture and in operating systems technology. This clears the way to using multiple processors. He briefly explains symmetric multiprocessing (SMP), where each processor shares the kernel image in memory and can execute its code concurrently, and asym-metric multiprocessing (ASMP), based on a masterlslave relationship between participating processors. The book also outlines the Sun solution for SMP: Sparc-CPU modules equipped with caches tied to an interconnect bus, to which 110 subsystem and physical memory connect separately. Next, the book describes the Sparc architecture and its unique register window model, compares versions 7, 8, and 9 of the Sparc specifications, and outlines Sparc chip imple-._______________~_ ~-mentations, including a brief note on Ultra-Sparc. It then outlines the Sparc memory model, explaining the differences between total-store ordering and partial-store ordering , and describes the memory management unit in detail. The next major subject is bus architectures. MBus (fully specified in the 58-page appendix) is a processor-to-memory bus, optimized for high-speed connection of the Sparc-CPU modules to physical memory and special U 0 modules. Its Level 2 protocol provides for cache-coherent shared-memory multipro-cessing and supports six transactions (ordinary read/write and four transactions supporting cache coherence: coherent read, coherent invalidate, coherent read & invalidate, and coherent write & invalidate). Its basic characteristics include multiplexed address/control with 64 bits of data and 36 bits of physical addressing, centralized arbitration, and up to 128-byte burst transfers. A chapter on designing shared-memory multiprocessor systems with MBus provides many useful details regarding cache-coherence protocols (mostly, MBus implementation of a …