Compact DC model of a JVeSFET transistor with reduced number of empirical parameters

M. Staniewski, A. Pfitzner
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引用次数: 1

Abstract

VeSTIC (Vertical-Slit Transistor based Integrated Circuit) architecture enables easy integration of all types of transistors on the same chip. One of the elements available in this technology is Junction Vertical-Slit Field-Effect Transistor (JVeSFET). Simulation based feasibility studies indicate that the device exhibit attractive electrical properties like DC characteristics of relatively low subthreshold slope and may be considered as a good candidate for applications requiring low-noise and radiation-tolerant performance. A compact model of JVeSFET suitable for circuit simulators has been developed in this paper1. It includes a reduced number of empirical fitting parameters and is accurate and universal enough to provide for changes of the basic material parameter of the device.
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减少经验参数数目的JVeSFET晶体管的紧凑直流模型
VeSTIC(垂直狭缝晶体管集成电路)架构可以在同一芯片上轻松集成所有类型的晶体管。该技术中可用的元件之一是结垂直狭缝场效应晶体管(JVeSFET)。基于仿真的可行性研究表明,该器件具有吸引人的电学特性,如相对较低的亚阈值斜率的直流特性,可以被认为是需要低噪声和耐辐射性能的应用的良好候选者。本文开发了一种适用于电路模拟器的紧凑的JVeSFET模型。它包括减少了经验拟合参数的数量,并且足够准确和通用,以提供设备的基本材料参数的变化。
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