A 2.5 Gbit/s pipelined routing engine for input-queued ATM switches

Abstract

This paper presents the design of a 2.5 Gbit/s pipelined virtual output queue routing engine for an input-queued ATM switch, which has a serial crossbar structure. The proposed routing engine has been designed for wire-speed routing with a pipelined buffer management. It provides the tolerance of requests and grants data transmission latency between the routing engine and central arbiter using a new request control method that is based on a high-speed shifter. The designed routing engine has been implemented in a field programmable gate array chip with a 77 MHz operating frequency, a 900-pin fine ball grid array package, and 16/spl times/16 switch size.