FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

N. Choudhary, Salil V. Wadhavkar, Tanmay A. Shah, Hiran Mayukh, Jayneel Gandhi, Brandon H. Dwiel, Sandeep Navada, H. H. Najaf-abadi, E. Rotenberg
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引用次数: 121

Abstract

A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-designed superscalar core types that can streamline the execution of diverse programs and program phases. No prior research has addressed the “Achilles' heel” of this paradigm: design and verification effort is multiplied by the number of different core types. This work frames superscalar processors in a canonical form, so that it becomes feasible to quickly design many cores that differ in the three major superscalar dimensions: superscalar width, pipeline depth, and sizes of structures for extracting instruction-level parallelism (ILP). From this idea, we develop a toolset, called FabScalar, for automatically composing the synthesizable register-transfer-level (RTL) designs of arbitrary cores within a canonical superscalar template. The template defines canonical pipeline stages and interfaces among them. A Canonical Pipeline Stage Library (CPSL) provides many implementations of each canonical pipeline stage, that differ in their superscalar width and depth of sub-pipelining. An RTL generation tool uses the template and CPSL to automatically generate an overall core of desired configuration. Validation experiments are performed along three fronts to evaluate the quality of RTL designs generated by FabScalar: functional and performance (instructions-per-cycle (IPC)) validation, timing validation (cycle time), and confirmation of suitability for standard ASIC flows. With FabScalar, a chip with many different superscalar core types is conceivable.
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在规范超标量模板内组合任意核的可合成RTL设计
越来越多的工作为单isa异构多核范式编写了强有力的案例。单个isa异构多核提供了多种不同设计的超标量核类型,可以简化不同程序和程序阶段的执行。之前没有研究解决过这个范例的“阿喀琉斯之踵”:设计和验证工作乘以不同核心类型的数量。这项工作将超标量处理器框架在一个规范的形式中,因此可以快速设计在三个主要超标量维度上不同的许多内核:超标量宽度、管道深度和用于提取指令级并行性(ILP)的结构大小。从这个想法出发,我们开发了一个工具集,称为FabScalar,用于在规范超标量模板内自动组合任意内核的可合成寄存器-传输级(RTL)设计。模板定义规范管道阶段和它们之间的接口。规范管道阶段库(CPSL)提供了每个规范管道阶段的许多实现,这些实现在子管道的超标量宽度和深度上有所不同。RTL生成工具使用模板和CPSL自动生成所需配置的整体核心。验证实验沿着三个方面进行,以评估由FabScalar生成的RTL设计的质量:功能和性能(每周期指令(IPC))验证,时间验证(周期时间),以及对标准ASIC流适用性的确认。有了FabScalar,一个有许多不同的超标量核心类型的芯片是可以想象的。
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