{"title":"Embedded reconfigurable DCT architectures using adder-based distributed arithmetic","authors":"A. Pai, K. Benkrid, D. Crookes","doi":"10.1109/CAMP.2005.23","DOIUrl":null,"url":null,"abstract":"A hybrid adder-based distributed arithmetic (DA) architecture targeting a reconfigurable system-on-chip (rSoC) platform has been presented. The work exemplifies hardware comparisons of three DA based discrete cosine transform (DCT) algorithms based on pure-RAM, mixed-RAM and CORDIC-based processors. Preliminary investigation involved evaluation of the DCT algorithms on a heterogeneous composition of domain-specific memory and logic building blocks. The architectures were simulated for functional validation on ModelSim SE v6.0 and compliance testing of these architectures was performed using a self-testing testbench. The motivation was to illustrate the modularity, regularity, symmetry, and recursive-decomposition properties of transform vector-matrix computations for a case study of discrete cosine transforms using adder-based DA. Further, the paper overviews existing DCT architectures and previews future reconfigurable computing devices and contributes towards a novel conjecture on future directions in the reconfigurable hardware landscape. The embedded reconfigurable computation array presented in this paper has an intermediate-grain framework unlike the fine-grained nature of the current FPGAs.","PeriodicalId":393875,"journal":{"name":"Seventh International Workshop on Computer Architecture for Machine Perception (CAMP'05)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2005-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Seventh International Workshop on Computer Architecture for Machine Perception (CAMP'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CAMP.2005.23","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A hybrid adder-based distributed arithmetic (DA) architecture targeting a reconfigurable system-on-chip (rSoC) platform has been presented. The work exemplifies hardware comparisons of three DA based discrete cosine transform (DCT) algorithms based on pure-RAM, mixed-RAM and CORDIC-based processors. Preliminary investigation involved evaluation of the DCT algorithms on a heterogeneous composition of domain-specific memory and logic building blocks. The architectures were simulated for functional validation on ModelSim SE v6.0 and compliance testing of these architectures was performed using a self-testing testbench. The motivation was to illustrate the modularity, regularity, symmetry, and recursive-decomposition properties of transform vector-matrix computations for a case study of discrete cosine transforms using adder-based DA. Further, the paper overviews existing DCT architectures and previews future reconfigurable computing devices and contributes towards a novel conjecture on future directions in the reconfigurable hardware landscape. The embedded reconfigurable computation array presented in this paper has an intermediate-grain framework unlike the fine-grained nature of the current FPGAs.
针对可重构的片上系统(rSoC)平台,提出了一种基于混合加法器的分布式算法(DA)架构。该工作举例说明了基于纯ram、混合ram和基于cordic处理器的三种基于DA的离散余弦变换(DCT)算法的硬件比较。初步的研究涉及对领域特定内存和逻辑构建块的异构组成的DCT算法的评估。在ModelSim SE v6.0上模拟这些体系结构以进行功能验证,并使用自测测试台执行这些体系结构的遵从性测试。动机是为了说明转换向量矩阵计算的模块化、规则性、对称性和递归分解性质,以使用基于加法器的DA进行离散余弦变换的案例研究。此外,本文概述了现有的DCT架构,并展望了未来的可重构计算设备,并对可重构硬件领域的未来方向做出了新的推测。本文提出的嵌入式可重构计算阵列具有中等粒度的框架,不同于当前fpga的细粒度特性。