Deployment of Braun Multiplier Using Novel Adder Formulations

Abstract

Latency and storage requirements are becoming increasingly important for all applications. One of the most crucial factors in industry is the time lag between production and consumption. These two factors are taken into account for any practical use in any sector. VLSI technology's many techniques allow for the creation of such software. Two approaches were taken in the creation of the Braun multiplier. This multiplier is built using a combination of CMOS and GDI techniques. The multiplier employs the parallel prefix adders. The system's speed may be increased with the use of the Braun multiplier. Tanner V-13 is the Electronic Design and Analysis tool used to create the Braun multiplier. Both complementary metal-oxide semiconductor and germanium-doped indium circuits took this multiplier's output into account.