{"title":"A New Hardware Architecture for the Ridge Regression Optical Flow Algorithm","authors":"Taylor Simons, Dah-Jye Lee","doi":"10.1109/SSIAI.2018.8470370","DOIUrl":null,"url":null,"abstract":"We present a new hardware architecture for calculating the optical flow of real time video streams. Our system produces dense motion fields in real time at high resolutions. We implemented a new version of the Ridge Regression Optical flow algorithm. This architecture design focuses on maximizing parallel operations of large amounts of pixel data and pipelining the data flow to allow for real time throughput. A specialized memory controller unit was designed to access pixel data from seven different frames. This memory control alleviates any memory bottleneck. The new architecture can process 1080p HD video streams at over 60 frames per second. This design requires no processor nor data bus which allows it to be more easily manufactured as an ASIC.","PeriodicalId":422209,"journal":{"name":"2018 IEEE Southwest Symposium on Image Analysis and Interpretation (SSIAI)","volume":"9 27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Southwest Symposium on Image Analysis and Interpretation (SSIAI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SSIAI.2018.8470370","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We present a new hardware architecture for calculating the optical flow of real time video streams. Our system produces dense motion fields in real time at high resolutions. We implemented a new version of the Ridge Regression Optical flow algorithm. This architecture design focuses on maximizing parallel operations of large amounts of pixel data and pipelining the data flow to allow for real time throughput. A specialized memory controller unit was designed to access pixel data from seven different frames. This memory control alleviates any memory bottleneck. The new architecture can process 1080p HD video streams at over 60 frames per second. This design requires no processor nor data bus which allows it to be more easily manufactured as an ASIC.