Settling-time-oriented design procedure for two-stage amplifiers with current-buffer Miller compensation

Abstract

A novel design procedure for two-stage operational amplifiers (op-amps) with current-buffer Miller compensation (CBMC) is proposed. The method is based on equations which relate both bias current and aspect ratio of transistors to the main amplifier parameters. The important innovation of the procedure is the definition of a systematic strategy to achieve the desired settling time by performing the op-amp dynamic behaviour optimization, which is badly needed in high-performance discrete-time applications. To prove the effectiveness of the proposed approach, a design example of a CBMC op-amp in 0.35 mum CMOS technology is presented.