Vertical Tunnel-FET Analysis for Excessive Low Power Digital Applications

Abstract

In this paper we study for the imminent novel Vertical Tunnel-FET(TFET) fascinating device for excessive low power digital circuit application because of its Subthreshold slope or swing (S) and low I-OFF current. As MOSFET are scaled down below the 45nm, the problems arises such as short channel effects, the I-OFF leakage current grow drastically because to the non-versatility of edge voltage as the Subthreshold Slope or swing (S) is restricted to 60mV/decade. As Tunnel FETs smothered the point of confinement of 60mV/decade by utilizing quantum-mechanical Band-2-Band Tunneling (B2BT) due to which the performance of this circuit for low power applications improved. This outline paper will examine about the substitution of the CMOS with different structures among which Vertical Tunnel Field Effect Transistor (TFET) found to be greater energy efficiency with improved $\mathrm{I}_{\mathrm{O}\mathrm{N}}$ current which is thought to be the most basic plan parameter for pervasive and portable processing frameworks.