Detailed modeling of fault-tolerant processor arrays

Abstract

Detailed modeling of fault-tolerant processor arrays entails not only an explosive growth in the model state space but also a difficult model construction process. The latter problem is addressed, and a systematic method to construct Markov models for evaluating the reliability of processor arrays is proposed. This method is based on the premise that the fault behavior of a processor array can be modeled by a stochastic Petri net. However, in order to obtain a more compact representation, a set of attributes is associated with each transition in the Petri net model. This set of attributes allows the construction of the corresponding Markov model as the generation of the reachability graph takes place. Included in these attributes is a discrete probability distribution such that the effect of faulty spares in the reconfiguration algorithm is captured each time a configuration change occurs. This distribution includes the probabilities of survival given that a number of components required by the reconfiguration process are faulty. Depending on the type of component and the reconfiguration scheme, probabilities of survival are determined using simulation or closed-form expressions.<>