Low Power RTL Exploration Mechanism Based on the Cache Parameters

Abstract

Cache memory is a usual architecture component, and has the function of increasing the system’s performance. Cache, however, may be responsible for a large part of energy consumption (about 50%) of microprocessors. Based on this, the paper proposes an automated architecture exploration mechanism based on parameter variation of a cache memory hierarchy and NIOS II processor. Results based on Mibench and XiRisc suite have demonstrated that, on average, with 12.5% of the design space, an energy consumption reduction of about 31% has been achieved, as well as an increase of 11% in the performance of the application. Additionally, it was observed that optimal results were found in 67% of the examined cases.