Design And Implementation of Low Power Phase Frequency Detector For Phase Lock Loop

Abstract

This paper presents a low power phase frequency detector for Phase lock loop. A presented Low power Phase Frequency Detector is implemented in Cadence virtuoso environment and using GPDK090 Library of 90nm CMOS Technology. The presented Phase Frequency Detector design has total 18 transistors, the total power consumption of the PFD is 10.85 uW@ .1GHz and almost zero dead zone. The occupied area of the presented PFD is 152.55um2 with 1V of supply voltage.