MOSFET optimization toward power efficient circuit design

A. Mukhopadhyay, S. Bhattacharya, T. Iizuka, T. Maiti, M. Miura-Mattausch, A. Gau, D. Navarro, H. Rahaman, A. Sengupta, S. Yoshitomi, H. Mattausch
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引用次数: 1

Abstract

The report focuses on an optimization scheme of advanced MOSFETs for designing power efficient circuits. For the purpose the physics-based compact model HiSIM2 is applied so that the relationship between device and circuit characteristics can be investigated properly. It is demonstrated that the short-channel effect, which is usually measured by the threshold-voltage shift compared to the long-channel MOSFET, provides the consistent measure as the short-channel effect on device performance degradation. However, the circuitry performances degradation such as the power loss cannot be predicted sufficiently by the short channel effect alone. It is demonstrated that the power efficient circuit design can be achieved by minimizing the additional leakage current caused by the short-channel contribution.
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面向功率高效电路设计的MOSFET优化
本报告的重点是一种先进的mosfet优化方案,用于设计功率高效电路。为此,应用基于物理的紧凑模型HiSIM2,以便可以适当地研究器件和电路特性之间的关系。研究表明,与长沟道MOSFET相比,通常通过阈值电压位移来测量的短沟道效应提供了短沟道效应对器件性能退化的一致测量。然而,仅靠短信道效应不能充分预测电路性能的退化,如功率损耗。结果表明,通过最小化由短通道贡献引起的额外漏电流,可以实现高效率的电路设计。
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