Design of Three-Valued Logic D-Latch Using GNRFET

Abstract

MVL is the promising alternative to the binary logic. GNRFET is more suitable for Multi-Valued Logic Circuits because it reduces power leakage, energy consumption. MVL logic provides less complexity, high speed circuit, small chip area in digital circuits. The GNRFETs are considered to regulate the Vth. Threshold voltage Vth control in GNRFET is possible by varying the width and no. of Dimer lines (N). In Ternary logic family there are 3 types of inverters Standard Ternary Inverter, Negative Ternary Inverter, Positive Ternary Inverter. To design ternary D-Latch NTI, STI, NAND gates are used. A latch is an electronic device, which changes its output based on the applied input. Latches are the smallest building blocks of memory. In the VLSI technology area, power consumption of the circuit is very important. In this paper, the performance of Three-Valued Logic D-Latch using GNRFET in terms of power, delay are calculated. The simulation of GNRFET based three valued logic D-Latch is done using HSPICE 32nm technology tool. It is observed that power is 20.60uW and delay is 150.04 ns.