High Performance 20-T based Hybrid Full Adder using 90nm CMOS Technology

Abstract

In this paper, a high-performance full adder design is proposed using the hybrid logic style. There are three modules in the hybrid logic structure. The module I generates the XOR/XNOR output simultaneously whereas module II and module III are realized using the XOR/XNOR and CIN signal. The proposed design is simulated in the cadence software using the 90 nm CMOS technology at 1.2V. The proposed design gives the improvement 53% and 57 % in terms of delay and PDP, respectively when compared with its best counterpart. The proposed circuit also performs well with different supply voltage.