{"title":"Design of high frequency phase locked loop","authors":"Raman Bondare, D. Bhoyar, C. Dethe, M. Mushrif","doi":"10.1109/ICCCCT.2010.5670772","DOIUrl":null,"url":null,"abstract":"A digital phase-locked loop (DPLL) is designed using 0.18 mm CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz-1 GHz. The DPLL operation includes two stages: (i) a novel coarse-tuning stage based on a flash algorithm, and (ii) a fine-tuning stage similar to conventional DPLLs. The flash portion of the DPLL is made up of frequency comparators, an encoder and a decoder which drives a multiple charge pump (CP)/low pass filter (LPF) combination. Design considerations of the flash DPLL circuit components as well as implementation using Tanner design tools are presented. Spectra simulations were also performed and demonstrated a significant improvement in the lock time of the flash DPLL as compared to the conventional DPLL.","PeriodicalId":250834,"journal":{"name":"2010 INTERNATIONAL CONFERENCE ON COMMUNICATION CONTROL AND COMPUTING TECHNOLOGIES","volume":"56 4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 INTERNATIONAL CONFERENCE ON COMMUNICATION CONTROL AND COMPUTING TECHNOLOGIES","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCCCT.2010.5670772","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A digital phase-locked loop (DPLL) is designed using 0.18 mm CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz-1 GHz. The DPLL operation includes two stages: (i) a novel coarse-tuning stage based on a flash algorithm, and (ii) a fine-tuning stage similar to conventional DPLLs. The flash portion of the DPLL is made up of frequency comparators, an encoder and a decoder which drives a multiple charge pump (CP)/low pass filter (LPF) combination. Design considerations of the flash DPLL circuit components as well as implementation using Tanner design tools are presented. Spectra simulations were also performed and demonstrated a significant improvement in the lock time of the flash DPLL as compared to the conventional DPLL.
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