CMOS differential pass-transistor logic (CMOS DPTL) predischarge buffer design

Abstract

In both NMOS and CMOS PTL techniques, the problem of noise immunity limits applications which suffer from relatively low logic swings. Noise voltages, can degrade system performance and even produce faulty circuit operation. So, we propose an alternative pass-transistor configurations that directly address noise-immunity. Differential Pass Transistor Logic (DPTL) is a powerful configuration in CMOS technology. DPTL buffers has the ability to generate standard CMOS levels regardless of input signal-swing variation while providing noise immunity by maintaining the structural symmetry.