Efficient flip-flop merging technique for clock power reduction

Abstract

Power reduction plays a vital role in VLSI design. Multi-bit flip-flop is an efficient method for clock power reduction. This method is to eliminate the redundant inverters by merging some flip-flops into multi-bit flip-flops. This multi-bit flip-flops can share the drive strength, dynamic power, area of the inverter chain and can even save the clock network power and facilitate the skew control. Firstly flip-flops that can be merged are identified based on synchronous clock signal and then a combination table is built to define the possible combination of flip-flops and finally a hierarchical way is used to merge flip-flops.