{"title":"MULTIPAR: an output queue ATM modular switch with multiple phases and replicated planes","authors":"Jian Ma, K. Rahko","doi":"10.1109/HPDC.1993.263846","DOIUrl":null,"url":null,"abstract":"The authors propose a novel output queuing ATM modular switch which has memoryless two-stage interconnection with disjoint-path topology. The goal of achieving the modular switch is to relax the limitation of VLSI implementation, to simplify interstage wiring and synchronization, furthermore to reduce complexity of the overall switch. A pure output queue is constructed by providing multipath in each output port and replicated switching module planes. The switch with certain cell loss requirement can be ensured by choosing a suitable path set of L/sub 1/ and L/sub 2/. For instance, cell loss probability in the switch can be kept less than 10/sup -6/ for various N, under 90% load, if a set of L/sub 1/=9 and L/sub 2/=4 (or L/sub 1/=8 and L/sub 2/=5) is chosen.<<ETX>>","PeriodicalId":226280,"journal":{"name":"[1993] Proceedings The 2nd International Symposium on High Performance Distributed Computing","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1993-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1993] Proceedings The 2nd International Symposium on High Performance Distributed Computing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HPDC.1993.263846","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The authors propose a novel output queuing ATM modular switch which has memoryless two-stage interconnection with disjoint-path topology. The goal of achieving the modular switch is to relax the limitation of VLSI implementation, to simplify interstage wiring and synchronization, furthermore to reduce complexity of the overall switch. A pure output queue is constructed by providing multipath in each output port and replicated switching module planes. The switch with certain cell loss requirement can be ensured by choosing a suitable path set of L/sub 1/ and L/sub 2/. For instance, cell loss probability in the switch can be kept less than 10/sup -6/ for various N, under 90% load, if a set of L/sub 1/=9 and L/sub 2/=4 (or L/sub 1/=8 and L/sub 2/=5) is chosen.<>
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