Equivalent circuit for parasitic coupling between plated through holes within PCB structures

Abstract

In this paper we present an equivalent circuit for simulating parasitic coupling between adjacent plated through holes, known as vias, within multilayer printed circuit boards (PCB's) and similar structures. This paper uses full wave 3D electromagnetic models and measurement results as part of the development of the equivalent circuit. We also demonstrate how the modelling and perhaps the equivalent circuit presented can be scaled to fit virtually any via geometries including Through Silicon Vias (TSVs) used in 3D IC packaging.