Evaluating high-speed link performance using direct end-to-end measurement

C. Ye, Kai Xiao, M. Johnston, Ricardo U. Chavez Cuadras, X. Ye
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引用次数: 1

Abstract

A measurement based methodology is introduced to evaluate die-to-die link performance for high-speed IOs. The die-to-die link is from TX silicon pad to RX pad and incorporates all the storage IO interconnect components. A BERT scope is used as the TX buffer driving signal into a bare chipset package at the bumps with adjustable TX jitter, Vswing, de-emphasis, etc. An oscilloscope is used as the RX buffer receiving signal at the hard disk drive pad with scope built-in features such as DFE and CTLE. This methodology can be used to evaluate link die-die to performance before silicon tape out, to de-couple system issues between silicon and interconnect, to provide input for new spec development, to correlate simulation and measurement and to explore solution space envelope. This method does not call for a specially designed test vehicles. Test examples are introduced for a 6Gbps link to demonstrate the methodology and to evaluate the interconnect healthiness.
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使用直接端到端测量评估高速链路性能
介绍了一种基于测量的方法来评估高速io的模对模链路性能。模对模链接是从TX硅垫到RX垫,并包含所有存储IO互连组件。BERT示波器用作TX缓冲区,将信号驱动到具有可调TX抖动,Vswing,去强调等凸起的裸芯片组封装中。示波器作为RX缓冲器在硬盘驱动器上接收信号,示波器内置功能如DFE和CTLE。该方法可用于在硅带出之前评估链接模具的性能,消除硅和互连之间的耦合系统问题,为新规格开发提供输入,关联模拟和测量以及探索解决方案空间包络。这种方法不需要专门设计的试验车辆。介绍了6Gbps链路的测试示例,以演示该方法并评估互连的健康性。
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