A bit swap logic (BSL) based bubble error correction (BEC) method for flash ADCs

Abstract

Flash type analog to digital converters (ADCs) have the highest speed amongst all the available ADCs because of their parallel architecture. The comparator outputs in a flash ADC are in the so-called `thermometer code' form. Because of device mismatch, clock jitter, offset voltage and metastability problems prevalent in a flash ADC, it suffers from bubble or sparkle error problem. This thus leads to an erroneous output code with consequent disastrous performance. Several researchers have attempted to overcome the bubble error problem with various bubble error correction (BEC) schemes but with limited success. An attempt has been made in this paper to correct the bubble error - the degree of correction vary from the first order to any higher order. Simulations have been carried out on the proposed circuit - both for first and second orders. It has been established that it requires lesser number of transistors and thus would consume less power.