A discussion on SRAM circuit design trend in deeper nano-meter era

Abstract

This paper describes the comparisons of area scaling trend of various SRAM margin-assist solutions for VT variability issues, which are based on efforts by not only the cell topology changes from 6 T to 8 T and 10 T but also incorporating multiple voltages supply for cell terminal biasing and timing sequence controls of read and write. The various solutions are analyzed in light of an impact of ever increasing VT variation (sigmaVT) on the required area overhead for each design solution, resulting in slowdown in the scaling pace. It has been found that 6 T will be allowed long reign even in 15 nm, if sigmaVT increasing pace is optimistically assumed, which sigmaVT can be suppressed to <70 mV even at 15 nm, thanks to EOT scaling for LSTP process, otherwise 10 T and 8 T with read modify write will be needed.